1. Field of the Invention
The present invention relates to a memory such as a ROM (read-only memory) or a DRAM (dynamic random-access memory).
2. Description of Related Art
FIG. 8 is a circuit diagram showing a part of a circuit configuration of a conventional memory. In this figure, the reference numerals 1 and 2 designate read bit lines, 3 and 4 designate read word lines to which read word select signals W.sub.1 and W.sub.2 are applied, respectively. The reference numerals 5 and 6 designate column select lines to which column select signals C.sub.1 and C.sub.2 are applied. The reference numerals 7 and 8 designate transistors connected in series with the read bit lines 1 and 2 for selecting the read bit lines 1 and 2, respectively. The transistor 7 and 8 have their gates connected to the column select lines 5 and 6, respectively.
The reference numeral 9 designates a common read bit line with its first end connected to the read bit lines 1 and 2 in common, and 10 designates a transistor for supplying charge to the common read bit line 9. The transistor 10 has its drain connected to the common read bit line 9 and its source connected to a supply voltage V.sub.DD. The reference numeral 11 designates an inverter whose input terminal is supplied with a chip enable control signal CEC and whose output terminal is connected to the gate of the transistor 10.
The reference numerals 12 and 13 designate inverters for amplifying the potential of the read bit lines 1 and 2. The inverter 12 has its input terminal connected to the common read bit line 9 and its output terminal to the input terminal of the inverter 13 which produces an output signal D.sub.0 from its output terminal. The reference numeral 14 designates a transistor for holding the input potential to the inverter 12. The transistor 14 has its gate connected to the output terminal of the inverter 12, its drain connected to the input terminal of the inverter 12, and its source connected to the supply voltage V.sub.DD.
The reference characters M.sub.1 -M.sub.4 designate transistors constituting the memory. The transistors M.sub.1 and M.sub.4 have their drains connected to the read bit lines 1 and 2, respectively. The transistors M.sub.2 and M.sub.3 have their sources open, and their drains connected to the read bit lines 2 and 1, respectively. In addition, the transistors M.sub.1 and M.sub.2 have their gates connected to the read word line 3, and the transistors M.sub.3 and M.sub.4 have their gates connected to the read word line 4.
FIG. 9 is a plan view showing the physical structure of the conventional memory in part, and FIG. 10 is a longitudinal sectional perspective view taken along the line B--B of FIG. 9. In FIGS. 9 and 10, portions corresponding to those of FIG. 8 are designated by the same reference numerals, and the description thereof is omitted here.
In FIGS. 9 and 10, the reference numerals 21 and 22 designate contact holes for contacting the metallic read bit lines 1 and 2 with the diffusion regions of the transistors M.sub.1 and M.sub.2, respectively, 23 designates a substrate, and 31 and 32 designate the diffusion regions of the transistors M.sub.1 and M.sub.2.
FIG. 11 is a timing chart illustrating waveforms of signals input to or output from the conventional memory. The operation of the memory will now be described with reference to the timing chart of FIG. 11.
First, the read bit line 2 is charged through transistors 10 and 8 during the interval in which the chip enable control signal CEC and the column select signal C.sub.2 are placed at a high level, so that the potential of the read bit line 2, which will be denoted as bit2, is placed at the high level. In the course of this, the potential of the read bit line 1, denoted as bit1, is in a floating state because the column select signal C.sub.1 is placed at a low level and hence the transistor 7 is nonconducting. The output signal D.sub.0 of the inverter 13 is at the high level because the high potential of the common read bit line 9 is inverted twice by the inverters 12 and 13.
When the column select signal C.sub.1 rises to the high level and the column select signal C.sub.2 falls to the low level in this state, the transistor 7 is turned on, and the transistor 8 is turned off. Accordingly, the potential bit1 rises to the high level so that the read bit line 1 is charged, and the potential bit2 is maintained at the high level.
When the chip enable control signal CEC falls in this state, the transistor 10 is turned off and the power supply to the common read bit line 9 is ceased. Subsequently, when the read word line select signal W.sub.1 rises, the transistors M.sub.1 and M.sub.2 conduct. Hence, the read bit line 1 is discharged through the transistor M.sub.1, and the potential bit1 and the output signal D.sub.0 fall to the low level. In this case, the potential bit1 gradually falls because the read bit line 1 is discharged rather slowly through the transistor M.sub.1.
Next, when the chip enable control signal CEC rises again, and the read word line select signal W.sub.1 falls, the transistor 10 is turned on and the transistors M.sub.1 and M.sub.2 are turned off, and the common read bit line 9 is supplied with the supply voltage V.sub.DD through the transistor 10. Since the transistor 7 is conducting and the transistor 8 is nonconducting in this case, the potential bit1 and the output signal D.sub.0 rise to the high level, again.
Even when the column select signal C.sub.1 falls to the low level and the column select signal C.sub.2 rises to the high level in this state, both the potentials bit1 and bit2 are kept at the high level because the potential bit1 has already been placed at the high level.
With such an arrangement, the time period taken by the output signal D.sub.0 to fall to the low level in the conventional memory is substantially determined by the discharge time through the transistor M.sub.1. Although increasing the size of the transistor M.sub.1 can shorten the fall time of the output signal D.sub.0, this will increase the size of the entire memory. Thus, there is a problem in that it is difficult to shorten the fall time of the output signal D.sub.0 without increasing the dimensions of the memory.